The present invention generally relates to increasing the system memory performance of a computer, and more particularly by enhancing the quality of the supply power fed to the system memory.
A trend in the computer industry has been the increase of the bus speed and all associated devices, primarily the interface between the main processor and the chipset including memory controller as well as the interface between the memory controller and the memory devices known as the memory bus. The memory devices are running at memory bus speed.
Aside from obvious speed issues that the memory devices can be subjected to, another concern relates to power draw of the individual devices as well as their aggregates in the form of memory modules. The power draw is proportional to the operating frequency, meaning that at lower operating frequencies, the devices will draw less power than at higher frequency. In addition to the raw issue of power draw, a major concern is the switching frequency of the devices, that is, how fast the transition from, e.g., a low power state in the form of active standby or even open page state to a four bank interleaved read occurs. The rapid switching between the different power states requires equally rapid switching capabilities of the power supply units as well as buffering capabilities of the entire voltage regulation module (VRM). The demand on the VRM increases with either overclocking or else increased system memory density, that is, more memory that needs to be powered. In this case, the state change of each module within the system can lead to interactions on the level of power supply between different modules, that can result in voltage peaks and valleys, either of which can adversely affect the operability and stability of all memory devices within the system.
Contemporary mainboard (motherboard) technology is using fast switching power management controllers that are supplemented by onboard capacitors for buffering of fast positive or negative voltage transients. Since the requirements for the circuitry lack detailed specifications it is up to the mainboard manufacturers to provide a solution deemed sufficient for delivering adequate supply and termination voltages. In most cases, the embodiment of choice is a single phase solution at minimum manufacturing cost. Despite the use of capacitors, this arrangement is not sufficient to provide optimal supply current to the memory devices, especially under load switching conditions.